BCM4339 Preliminary Data Sheet
List of Figures
Figure 36: WLAN PHY Block Diagram............................................................................................................. 91
Figure 37: Radio Functional Block Diagram .................................................................................................... 93
Figure 38: 160-Ball FCFBGA (Top View)......................................................................................................... 94
Figure 39: 145-Ball WLBGA (Top View) .......................................................................................................... 95
Figure 40: 286-Bump WLCSP (Bottom View).................................................................................................. 96
Figure 41: Port Locations for Bluetooth Testing............................................................................................. 126
Figure 42: Port Locations Showing Optional ePA and eLNA (Applies to 2.4 GHz and 5 GHz) ..................... 138
Figure 43: SDIO Bus Timing (Default Mode) ................................................................................................. 159
Figure 44: SDIO Bus Timing (High-Speed Mode).......................................................................................... 161
Figure 45: SDIO Clock Timing (SDR Modes) ................................................................................................ 162
Figure 46: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 163
Figure 47: SDIO Bus Output Timing (SDR Modes up to 100 MHz)............................................................... 164
Figure 48: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)..................................................... 164
Figure 49: ∆tOP Consideration for Variable Data Window (SDR 104 Mode) ................................................ 165
Figure 50: SDIO Clock Timing (DDR50 Mode).............................................................................................. 166
Figure 51: SDIO Data Timing (DDR50 Mode) ............................................................................................... 167
Figure 52: gSPI Timing .................................................................................................................................. 168
Figure 53: WLAN = ON, Bluetooth = ON ....................................................................................................... 173
Figure 54: WLAN = OFF, Bluetooth = OFF.................................................................................................... 173
Figure 55: WLAN = ON, Bluetooth = OFF ..................................................................................................... 174
Figure 56: WLAN = OFF, Bluetooth = ON .................................................................................................... 174
Figure 57: 160-Ball FCFBGA Package Mechanical Information.................................................................... 176
Figure 58: 145-Ball WLBGA Package Mechanical Information ..................................................................... 177
Figure 59: WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up............................ 178
Figure 60: 286-Bump WLCSP Package Mechanical Information .................................................................. 179
Figure 61: WLCSP Keep-out Areas for PCB Layout—Bottom View with Bumps Facing Up......................... 180
Broadcom®
November 17, 2014 • 4339-DS106-R
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