BCM4339 Preliminary Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 2
Figure 2: BCM4339 Block Diagram ................................................................................................................. 21
Figure 3: Typical Power Topology for BCM4339 ............................................................................................. 26
Figure 4: Recommended Oscillator Configuration ........................................................................................... 30
Figure 5: Recommended Circuit to Use with an External Reference Clock..................................................... 31
Figure 6: Startup Signaling Sequence ............................................................................................................. 42
Figure 7: CVSD Decoder Output Waveform Without PLC............................................................................... 44
Figure 8: CVSD Decoder Output Waveform After Applying PLC..................................................................... 44
Figure 9: Functional Multiplex Data Diagram................................................................................................... 50
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode).............................................................. 51
Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)................................................................ 52
Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 53
Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 54
Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync)......................................................... 55
Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 56
Figure 16: USB Compounded Device Configuration ....................................................................................... 57
Figure 17: USB Full-Speed Timing .................................................................................................................. 59
Figure 18: UART Timing .................................................................................................................................. 60
Figure 19: I2S Transmitter Timing.................................................................................................................... 63
Figure 20: I2S Receiver Timing........................................................................................................................ 63
Figure 21: Example Blend/Switch Usage......................................................................................................... 66
Figure 22: Example Blend/Switch Separation.................................................................................................. 67
Figure 23: Example Soft Mute Characteristic .................................................................................................. 68
Figure 24: Broadcom GCI or BT-SIG Mode LTE Coexistence Interface for BCM4339 ................................... 71
Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 74
Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 74
Figure 27: Signal Connections to SDIO Host (gSPI Mode) ............................................................................. 75
Figure 28: gSPI Write Protocol ........................................................................................................................ 76
Figure 29: gSPI Read Protocol ........................................................................................................................ 76
Figure 30: gSPI Command Structure............................................................................................................... 77
Figure 31: gSPI Signal Timing Without Status (32-bit Big Endian).................................................................. 78
Figure 32: gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian) ..................................... 79
Figure 33: WLAN Boot-Up Sequence.............................................................................................................. 82
Figure 34: PCI Express Layer Model............................................................................................................... 83
Figure 35: WLAN MAC Architecture ................................................................................................................ 86
Broadcom®
November 17, 2014 • 4339-DS106-R
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