ADVANCE
CYW4356
2.3 WLAN Power Management
The CYW4356 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip
design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and
supply voltages. Additionally, the CYW4356 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply
current consumed by the RAM is leakage current only. Additionally, the CYW4356 includes an advanced WLAN power management
unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4356 into various power
management states appropriate to the current environment and activities that are being performed. The power management unit
enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table
that describes the relationship between resources and the time needed to enable and disable them. Power up sequences are fully
programmable. Configurable, free-running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/
turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode.
Slower clock speeds are used wherever possible.
The CYW4356 WLAN power states are described as follows:
■ Active mode—All WLAN blocks in the CYW4356 are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■ Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. All main
clocks (PLL, crystal oscillator, or TCXO) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is
available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition
to Active mode. Logic states in the digital core are saved and preserved into a retention memory in the always-ON domain before
the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resumes through
the SDIO bus and logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization.
In Deep-sleep mode, the primary source of power consumption is leakage current.
■ Power-down mode—The CYW4356 is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic reenabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources
based on a computation of the required resources and a table that describes the relationship between resources and the time needed
to enable and disable them.
Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the
resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value
of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz
PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is
0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go
immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or
the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■ Computes the required resource set based on requests and the resource dependency table.
■ Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
■ Compares the request with the current resource status and determines which resources must be enabled or disabled.
■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.
■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
Document Number: 002-15053 Rev. *D
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