ADVANCE
CYW4356
Figure 3. Typical Power Topology for the CYW4356
1.2V
Internal LNLDO
WL RF – AFE
1.2V
Internal LNLDO
WL RF – TX (2.4 GHz, 5 GHz)
1.2V
WL RF – LOGEN (2.4 GHz, 5 GHz)
WL RF – RX/LNA (2.4 GHz, 5 GHz)
Internal VCOLDO
1.2V
Internal LNLDO
XTAL LDO
30 mA
1.2V
1.2V
WL RF – XTAL
WL RF – RFPLL PFD/MMD
LNLDO
Max. 150 mA
BT RF/FM
DFE/DFLL
WL_REG_ON
BT_REG_ON
PCIE PLL/RXTX
Core Buck
Regulator
CBUCK
WLAN BBPLL/DFLL
WLAN/BT/CLB/Top, Always‐on
VBAT
1.35V
Mx. 600 mA
WL OTP
WL PHY
CLDO
Max. 300 mA
(Bypass in deep
sleep)
1.1V
LPLDO1
3 mA
1.2V–1.1V
VDDIO
WL DIGITAL
BT DIGITAL
WL/BT SRAMs
2.5V
3.3V
3.3V
BTLDO2P5
Max. 70 mA
BT CLASS 1 PA
WL RF‐PA (2.4 GHz, 5 GHz)
WL PAD (2.4 GHz, 5 GHz)
VDDIO_RF
LDO3P3
Max. 600 mA
WL OTP 3.3V
LDO3P3_B
Max. 150 mA
WL RF – VCO
WL RF – CP
Internal LNLDO
Internal LNLDO
Document Number: 002-15053 Rev. *D
Page 11 of 155
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