BCM4330 Preliminary Data Sheet
Signal Assignments
12
11
10
9
8
7
6
5
4
3
2
1
BT_
VCOVDD1P2
BT_
PAVDD3P3
WRF_
RFOUT_2G
WRF_
RFOUT_5G
FM_AOUT1
BT_FEVSS
BT_RF
WRF_RFIN_2G
WRF_VDDPA
A
B
C
D
E
A
B
C
D
E
BT_
PLLVDD1P2
WRF_VDDLNA
_1P2_2G
WRF_
PA_GND
WRF_
RFIN_5G
FM_AOUT2
FM_TX
BT_RFVSS BT_RFVDD1P2 BT_IFVDD1P2
WRF_PA_GND
WRF_PA_GND
FM_
VSSAUDIO
WRF_
GNDLNA_2G
WRF_PADRV_
GND
WRF_
PADRV_VDD
WRF_
ANA_GND
BT_PLLVSS
BT_VSS
BT_IFVSS
WRF_GND
WRF_
LOGEN_A
_GND
WRF_
LOGEN_A_
VDD1P2
FM_
VDDAUDIO
BT_
BT_
WRF_A_
TSSI_IN
WRF_
VDDANA_1P2
FM_RXN
FM_RXP
BT_GPIO_1 WL_GPIO_6
BT_
WL_GPIO_3
CLK_REQ_IN UART_TXD
FM_
RFVDD1P2
FM_
VDDPLL1P2
WRF_
GPIO_OUT
WRF_VDD_VC
OLDO_IN_1P8
FM_RXVSS
CLK_REQ_
MODE
BT_VDDC
WL_VDDC BT_UART_RXD WL_VSS_2
BT_UART_
WRF_RES_EXT
WRF_
AFE_GND
WRF_
TCXO_VDD
WRF_VCOLDO
_OUT_1P2
WRF_
VCO_GND
FM_VDD2P5 FM_VSSVCO FM_PLLVSS BT_GPIO_0
BT_VSSC
BT_VDDIO
JTAG_SEL
F
F
RTS_N
BT_CLK_REQ_
BT_UART_
CTS_N
WRF_
VDDAFE_1P2
WRF_
TCXO_IN
WRF_
XTAL_OP
BT_TM0
BT_RST_N
BT_GPIO_7
BT_I2S_DI
WL_GPIO_1
G
H
J
G
H
J
OUT
WRF_
WRF_
XTAL_GND
WRF_
XTAL_ON
BT_GPIO_4
BT_GPIO_2 BT_GPIO_3 BT_GPIO_6 BT_I2S_DO BT_PCM_CLK WL_GPIO_2 WL_GPIO_0 XTAL_VDD
1P2
EXT_PWM_
REQ
RF_SW_
CTRL_5
RF_SW_
CTRL_6
RF_SW_
CTRL_1
VOUT_3P3
VOUT_3P1
BT_GPIO_5 WL_GPIO_4
LPO
BT_PCM_IN BT_PCM_OUT
HSIC_RREF
WL_VDDC
EXT_SMPS_
BT_VDDC
REQ
BT_PCM_
SYNC
RF_SW_
CTRL_0
RF_SW_
CTRL_7
RF_SW_
CTRL_4
SR_VDDBAT1 SR_VDDBAT2 BT_REG_ON
WL_VDDC
WL_VSS_0
K
L
K
L
VOUT_
SR_VDDBAT1 PMU_AVSS
LNLDO1
RF_SW_
CTRL_2
WL_REG_ON SDIO_DATA_3 SDIO_CMD WL_GPIO_5 WL_VSS_1
VOUT_CLDO SDIO_DATA_1 SDIO_CLK SDIO_DATA_0 SDIO_DATA_2
VDDIO_RF
HSIC_DATA HSIC_AVDD12
RF_SW_
CTRL_3
SR_VLX
SR_PVSS
VIN_LDO
WL_VDDO HSIC_STROBE HSIC_AVSS
M
M
12
11
10
9
8
7
6
5
4
3
2
1
Figure 39: 133-WLBGA Ball Map (bottom view)
®
BROADCOM
BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 96
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