BCM4330 Preliminary Data Sheet
PCM Interface
Long Frame Sync, Slave Mode
1
2
3
PCM_BCLK
4
5
PCM_SYNC
9
PCM_OUT
PCM_IN
Bit 0
Bit 0
HIGH IMPEDANCE
8
Bit 1
6
7
Bit 1
Figure 15: PCM Timing Diagram (Long Frame Sync, Slave Mode)
Table 8: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Ref No. Characteristics
Minimum Typical Maximum Unit
1
2
3
4
5
6
7
8
9
PCM bit clock frequency
–
41
41
8
8
0
8
8
0
–
–
–
–
–
–
–
–
–
12
–
–
–
–
25
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
PCM bit clock HIGH
PCM bit clock LOW
PCM_SYNC setup
PCM_SYNC hold
PCM_OUT delay
PCM_IN setup
PCM_IN hold
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
25
®
BROADCOM
BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 58
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