BCM4330 Preliminary Data Sheet
PCM Interface
Long Frame Sync, Master Mode
1
2
3
PCM_BCLK
4
PCM_SYNC
8
PCM_OUT
HIGH IMPEDANCE
7
Bit 0
Bit 1
Bit 1
5
6
Bit 0
PCM_IN
Figure 14: PCM Timing Diagram (Long Frame Sync, Master Mode)
Table 7: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Ref No. Characteristics
Minimum Typical Maximum Unit
1
2
3
4
5
6
7
8
PCM bit clock frequency
PCM bit clock HIGH
PCM bit clock LOW
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
PCM_IN hold
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
–
41
41
0
0
8
–
–
–
–
–
–
–
–
12
–
–
25
25
–
MHz
ns
ns
ns
ns
ns
ns
ns
8
0
–
25
®
BROADCOM
BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 57
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