BCM4319 Preliminary Data Sheet
gSPI
Command Structure
The SPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 11.
Figure 11: SPI Command Structure
BCM_SPID Command Structure
27
31 30 29 28
11 10
0
C
A
F1 F0
Address – 17 bits
Packet length - 11bits *
* 11’h0 = 2048 bytes
Function No: 00 – Func 0: All SPI specific registers
01 – Func 1: Registers and meories belonging to other blocks in the chip (64 bytes max)
10 – Func 2: DMA channel 1. WLAN packets up to 2048 bytes.
11 – Func 3: DMA channel 2 (optional). Packets up to 2048 bytes.
Access : 0 – Fixed address
1 – Incremental address
Command : 0 – Read
1 – Write
Write
The host puts the first bit of the data onto the bus one-half clock-cycle before the first active edge following the
CS going low. The following bits are clocked out on the falling edge of the SPI clock. The device samples the
data on the active edge.
Write-Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the
first rising clock edge of the clock burst for the data. The last clock edge of the fixed delay word can be used to
represent the first bit of the following data word. This allows data to be ready for the first clock edge without
relying on asynchronous delays.
Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs
from the write-read command in the following respects: a) chip selects go high between the command/address
and the data and b) the time interval between the command/address is not fixed.
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 30
April 2, 2014 • 4319-DS05-R
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