BCM4319 Preliminary Data Sheet
USB 2.0 and SDIO Interfaces
Section 5: USB 2.0 and SDIO Interfaces
USB 2.0 Device Core
The USB 2.0 device core is enabled by a strapping option, see Table 8 on page 56 for details. It includes the
following features: includes the following features:
•
Support for high speed at 480 Mbit/s or full speed at 12 Mbit/s operation
– USB 2.0 transceiver interface
– Data and clock recovery circuit
– Bit stuffing and unstuffing; bit stuff error detection
– SYNC/EOP generation and checking
– Error detection and handling
– Wake up, resume, and suspend detection
•
•
Endpoint management unit–Manages USB traffic and DMA engine
USB 2.0 protocol engine
– Parallel interface engine (PIE) between packet buffers and USB transceiver
– Supports up to nine endpoints, including Configurable Control Endpoint 0
Separate endpoint packet buffers, each with a 512-byte first-in first-out (FIFO) buffer
Host-to-device communication for bulk, control, and interrupt transfers
Configuration/status registers
•
•
•
The blocks in the USB 2.0 device core are shown in Figure 7.
Figure 7: USB 2.0 Device Block Diagram
32-Bit On-Chip Communication System
DMA Engines
s
F O F X I T
F O F X I T
F O F I T X
F I O s F T X
F O F I T X
s
s
s
RX FIFO
TX FIFOs
Endpoint Management Unit
USB 2.0 Protocol Engine
USB 2.0 PHY
USB 2.0 Device
D +
D -
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 26
April 2, 2014 • 4319-DS05-R
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