BCM4319 Preliminary Data Sheet
gSPI
Figure 13: SPI Signal Timing with Status (Response Delay = 0)
cs
sclk
Write
mosi
CC3311
CC11
CC00 DD3311
DD11
DD00
SS3311
SS11
SS00
miso
Command 32 bits
Write Data 16*n bits
Status 32 bits
Write-Read
cs
sclk
mosi
miso
CC3311
CC00
DD3311
DD11
DD00 SS3311
Status 32 bits
SS00
Read Data 16*n bits
Command 32 bits
Read
cs
sclk
mosi
miso
CC3311
CC00
DD3311
DD11
DD00 SS3311
SS00
Command 32 bits
Read Data 16*n bits
Status 32 bits
Table 2: SPI Status Field Details
Description
Bit
Name
0
1
Data not available
Underflow
The requested read data is not available
FIFO underflow occurred due to current (F2, F3) read
command
2
Overflow
FIFO overflow occurred due to current (F1, F2, F3) write
command
3
F2 interrupt
F2 channel interrupt
4
F3 interrupt
F3 channel interrupt
5
F2 RX Ready
F2 FIFO is ready to receive data (FIFO empty)
F3 FIFO is ready to receive data (FIFO empty)
–
6
F3 RX Ready
7
Reserved
8
F2 Packet Available
F2 Packet Length
F3 Packet Available
F3 Packet Length
Packet is available/ready in F2 TX FIFO
Length of packet available in F2 FIFO
Packet is available/ready in F3 TX FIFO
Length of packet available in F3 FIFO
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Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 32
April 2, 2014 • 4319-DS05-R
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