CYW20738
Table 21. SPI1 Timing Values—SCLK = 6 MHz and VDDM = 1.62Va
Reference
Characteristics
Symbol
Min
Typicalb
Max Unit
1
Output setup time, from MOSI data valid to
sample edge of SCLK
Tds_mo
–
–
41
–
ns
2
Output hold time, from sample
Tdh_mo
120
–
ns
edge of SCLK to MOSI data update
3c
4c
Time from CS assert to first SCLK edge
Time from first SCLK edge to CS deassert
Tsu_cs
Thd_cs
½ SCLK period – 1
½ SCLK period
–
–
–
–
ns
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as
low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled.
Table 22. SPI2 Timing Values—SCLK = 12 MHz and VDDM = 3.2Va
Reference
Characteristics
Symbol
Min
Typicalb
Max Unit
1
Output setup time, from MOSI
data valid to sample edge of SCLK
Tds_mo
–
–
26
–
ns
2
Output hold time, from sample
Tdh_mo
56
–
ns
edge of SCLK to MOSI data update
3c
4c
Time from CS assert to first SCLK edge
Time from first SCLK edge to CS deassert
Tsu_cs
Thd_cs
½ SCLK period – 1
½ SCLK period
–
–
–
–
ns
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as
low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
Table 23. SPI2 Timing Values—SCLK = 6 MHz and VDDM = 1.62Va
Reference
Characteristics
Symbol
Min
Typicalb
Max Unit
1
Output setup time, from MOSI
data valid to sample edge of SCLK
Tds_mo
–
50
–
ns
2
Output hold time, from sample
edge of SCLK to MOSI data update
Tdh_mo
–
120
–
ns
3c
4c
Time from CS assert to first SCLK edge
Time from first SCLK edge to CS deassert
Tsu_cs
Thd_cs
½ SCLK period – 1
½ SCLK period
–
–
–
–
ns
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as
low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
Document Number: 002-14891 Rev. *C
Page 34 of 42
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