CYW20738
3.3.2 SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when
2.2V ≥ VDDIO ≥ 1.62V.
Figure 12 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in Table 20, Table 21 on
page 34, Table 22 on page 34, Table 23 on page 34.
Figure 12. SPI Timing Diagram
3
4
CS
SCLK
Mode 1
SCLK
Mode 3
2
1
MSB
MSB
LSB
LSB
MOSI
MISO
Invalid bit
Table 20. SPI1 Timing Values—SCLK = 12 MHz and VDDM = 3.2Va
Reference
Characteristics
Symbol
Min
Typicalb
Max Unit
1
Output setup time, from MOSI
data valid to sample edge of SCLK
Tds_mo
–
20
–
ns
2
Output hold time, from sample
edge of SCLK to MOSI data update
Tdh_mo
–
63
–
ns
3c
4c
Time from CS assert to first SCLK edge
Tsu_cs
½ SCLK period – 1
½ SCLK period
–
–
–
–
ns
ns
Time from first SCLK edge to CS deassert Thd_cs
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as
low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled.
Document Number: 002-14891 Rev. *C
Page 33 of 42
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