CYW20738
1.8 Microprocessor Unit
The CYW20738 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer components
that ensure adherence to the Bluetooth Human Interface Device (HID) profile. The microprocessor is based on an ARM Cortex™-M3,
32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The µPU has 320 KB of ROM for program storage
and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code.
The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different Bluetooth HID over
GATT applications with an external serial EEPROM or with an external serial flash memory for application and patch storage. At
power-up, the lowest layer of the protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
1.8.1 EEPROM Interface
The CYW20738 provides a Broadcom Serial Control (BSC) master interface. The BSC is programmed by the CPU to generate four
types of BSC bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and
fast mode devices. The BSC is compatible with a Philips® (now NXP) I2C slave device, except that master arbitration (multiple I2C
masters contending for the bus) is not supported.
The EEPROM can contain customer application configuration information including: application code, configuration data, patches,
pairing information, BD_ADDR, and file system information used for code.
Native support for the Microchip® 24LC128, Microchip 24AA128, and ST Micro® M24128-BR is included.
1.8.2 Serial Flash Interface
The CYW20738 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Devices natively supported include the following:
■ Atmel® AT25DF011-MAHN
1.8.3 Internal Reset
Figure 4. Internal Reset Timing
VDDO POR delay
~ 2 ms
VDDO
VDDO POR threshold
VDDO POR
VDDC POR threshold
VDDC
VDDC POR delay
~ 2 ms
VDDC POR
Crystal
warm-up
delay:
~ 5 ms
Baseband Reset
Start reading EEPROM and firmware boot
Crystal Enable
Document Number: 002-14891 Rev. *C
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