CYW20737
3.3.3 BSC Interface Timing
Table 22. BSC Interface Timing Specifications
Reference
Characteristics
Min
Max
100
Unit
kHz
1
Clock frequency
–
400
800
1000
–
2
START condition setup time
START condition hold time
Clock low time
650
280
650
280
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
–
4
–
5
Clock high time
–
6
Data input hold timea
Data input setup time
STOP condition setup time
Output valid from clock
Bus free timeb
–
7
100
280
–
–
8
–
9
400
–
10
650
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions.
b. Time that the cbus must be free before a new transaction can start.
Figure 13. BSC Interface Timing Diagram
Document Number: 002-16365 Rev. *C
Page 29 of 36
CYPRESS [ CYPRESS ]
