CYW20737
3.3.2 SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when 2.2V > VDDIO
≥ 1.62V.
Figure 11 and Figure 12 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively.
Table 21. SPI Interface Timing Specifications
Reference
Characteristics
Time from CSN asserted to first clock edge
Master setup time
Min
1 SCK
Typ
Max
1
2
3
4
5
6
100
∞
–
–
½ SCK
–
Master hold time
½ SCK
–
–
Slave setup time
½ SCK
–
–
Slave hold time
½ SCK
1 SCK
–
Time from last clock edge to CSN deasserted
10 SCK
100
Figure 11. SPI Timing – Mode 0 and 2
6
SPI_CSN
SPI_CLK
1
(Mode 0)
SPI_CLK
(Mode 2)
2
3
‐
First Bit
Second Bit
Last bit
‐
SPI_MOSI
SPI_MISO
4
5
First Bit
Not Driven
Second Bit
Last bit
Not Driven
Figure 12. SPI Timing – Mode 1 and 3
6
SPI_CSN
SPI_CLK
1
(Mode 1)
SPI_CLK
(Mode 3)
2
3
‐
Invalid bit
Invalid bit
‐
First bit
Last bit
SPI_MOSI
SPI_MISO
4
5
Not Driven
Not Driven
First bit
Last bit
Document Number: 002-16365 Rev. *C
Page 28 of 36
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