BCM20730 Data Sheet
Timing and AC Characteristics
a
Table 22: SPI2 Timing Values—SCLK = 6 MHz and VDDM = 1.62V
b
Reference Characteristics
Symbol
Min
Typical
Max Unit
1
2
3
4
Output setup time, from MOSI
Tds_mo
–
50
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
data valid to sample edge of SCLK
Output hold time, from sample
edge of SCLK to MOSI data update
Tdh_mo
Tds_mi
Tdh_mi
Tsu_cs
–
120
TBD
TBD
–
Input setup time, from MISO
data valid to sample edge of SCLK
–
Input hold time, from sample
edge of SCLK to MISO data update
–
c
c
Time from CS assert to first SCLK
edge
½ SCLK period – 1
½ SCLK period
5
6
Time from first SCLK edge to CS
deassert
Thd_cs
–
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
BSC Interface Timing
Table 23: BSC Interface Timing Specifications
Reference
Characteristics
Min
Max
Unit
1
Clock frequency
–
100
400
800
1000
–
kHz
2
START condition setup time
START condition hold time
Clock low time
650
280
650
280
0
100
280
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
–
–
–
Clock high time
a
6
7
8
Data input hold time
–
–
–
Data input setup time
STOP condition setup time
Output valid from clock
9
10
400
–
b
Bus free time
650
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid
unintended generation of START or STOP conditions.
b. Time that the cbus must be free before a new transaction can start.
BROADCOM
®
September 9, 2013 • 20730-DS108-R
Page 51
BROADCOM CONFIDENTIAL
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