BCM20730 Data Sheet
Timing and AC Characteristics
a
Table 20: SPI1 Timing Values—SCLK = 6 MHz and VDDM = 1.62V
b
Reference Characteristics
Symbol
Min
Typical
Max Unit
1
2
3
4
Output setup time, from MOSI data Tds_mo
valid to sample edge of SCLK
–
41
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
Output hold time, from sample
edge of SCLK to MOSI data update
Tdh_mo
Tds_mi
Tdh_mi
Tsu_cs
–
120
TBD
TBD
–
Input setup time, from MISO
data valid to sample edge of SCLK
–
Input hold time, from sample
edge of SCLK to MISO data update
–
c
c
Time from CS assert to first SCLK
edge
½ SCLK period – 1
½ SCLK period
5
6
Time from first SCLK edge to CS
deassert
Thd_cs
–
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled.
a
Table 21: SPI2 Timing Values—SCLK = 12 MHz and VDDM = 3.2V
b
Reference Characteristics
Symbol
Min
Typical
Max Unit
1
2
3
4
Output setup time, from MOSI
Tds_mo
–
26
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
data valid to sample edge of SCLK
Output hold time, from sample
edge of SCLK to MOSI data update
Input setup time, from MISO
data valid to sample edge of SCLK
Input hold time, from sample
edge of SCLK to MISO data update
Time from CS assert to first SCLK
edge
Time from first SCLK edge to CS
deassert
Tdh_mo
Tds_mi
Tdh_mi
Tsu_cs
–
56
TBD
TBD
–
–
–
c
c
½ SCLK period – 1
½ SCLK period
5
6
Thd_cs
–
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
BROADCOM
®
September 9, 2013 • 20730-DS108-R
Page 50
BROADCOM CONFIDENTIAL
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