The EZ-USB oscillator re-starts when:
•
•
USB bus activity resumes (shown as “USB Resume” in Figure 11-3), or
External logic asserts the EZ-USB WAKEUP# pin low.
After an oscillator stabilization time, the EZ-USB core asserts the 8051 Resume interrupt
(Figure 9-1). This causes the 8051 to exit its idle mode. The Resume interrupt is the high-
est priority 8051 interrupt. It is always enabled, unaffected by the EA bit.
The resume ISR clears the interrupt request flag, and executes an “reti” (return from inter-
rupt) instruction. This causes the 8051 to continue program execution at the instruction
following the one that set PCON.0 to initiate the suspend operation.
About the ‘Resume’ Interrupt
The 8051 enters the idle mode when PCON.0 is set to “1.” Although the 8051 exits its
idle state when any interrupt occurs, the EZ-USB logic supports only the RESUME inter-
rupt for the USB resume operation. This is because the EZ-USB core asserts this partic-
ular interrupt after restarting the 8051 clock.
11.4 Remote Wakeup
USBCS
USB Control and Status
7FD6
b7
b6
b5
b4
b3
b2
b1
b0
WAKESRC
-
-
-
DISCON
DISCOE
RENUM SIGRSUME
Figure 11-4. USB Control and Status Register
Two bits in the USBCS register are used for remote wakeup, WAKESRC and SIGR-
SUME.
After exiting the idle state, the 8051 reads the WAKESRC bit in the USBCS register to
discover how the wakeup was initiated. WAKESRC=1 indicates assertion of the
WAKEUP# pin, and WAKESRC=0 indicates a resumption of USB bus activity. The 8051
clears the WAKESRC bit by writing a “1” to it.
Page 11-4
Chapter 11. EZ-USB Power Management
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
