8.6.2 Fast Reads
DPTR
ISO IN FIFO
FRD#
D[7..0]
External FIFO
or ASIC
Accumulator
Figure 8-9. Fast Transfer, Outside Memory to EZ-USB
Fast reads are illustrated in Figure 8-9. When the fast mode is enabled, the DPTR points
to an isochronous OUT FIFO register, and the 8051 executes the “movx @dptr,a” instruc-
tion, the EZ-USB core breaks the data path from the accumulator to the IN FIFO register,
and instead writes the IN FIFO using outside data from D[7..0]. The EZ-USB core syn-
chronizes this transfer by generating a FIFO Read Strobe FRD# (Fast Read). A choice of
eight waveform is available for the read strobe, as shown in the next section.
8.7
Fast Transfer Timing
The 8051 sets bits in the FASTXFR register to select the fast ISO and/or fast BULK mode
and to adjust the timing and polarity of the read and write strobes FRD# and FWR#.
FASTXFR
Fast Transfer Control
7FE2
b7
b6
b5
b4
b3
b2
b1
b0
WMOD0
FISO
FBLK
RPOL
RMOD1
RMOD0
WPOL
WMOD1
Figure 8-10. The FASTXFR Register Controls FRD# and FWR# Strobes
The 8051 sets FISO=1 to select the fast ISO mode and FBLK=1 to select the fast Bulk
mode. The 8051 selects read and write strobe pulse polarities with the RPOL and WPOL
bits, where 0=active low, and 1=active high. Read and write strobe timings are set by
EZ-USB TRM v1.9
Chapter 8. EZ-USB CPU
Page 8-11
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