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AN2131QC 参数 Datasheet PDF下载

AN2131QC图片预览
型号: AN2131QC
PDF下载: 下载PDF文件 查看货源
内容描述: 在EZ - USBTM集成电路 [The EZ-USBTM Integrated Circuit]
分类和应用:
文件页数/大小: 334 页 / 1468 K
品牌: CYPRESS [ CYPRESS ]
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7.3.12 Firmware Load  
The USB endpoint zero protocol provides a mechanism for mixing vendor-specific  
requests with the previously described standard device requests. Bits 6:5 of the bmRe-  
quest field are set to 00 for a standard device request, and to 10 for a vendor request.  
Table 7-21. Firmware Download  
Byte  
0
Field  
bmRequestType  
bRequest  
wValueL  
Value  
Meaning  
8051 Response  
0x40 Vendor Request, OUT None required  
1
0xA0 Firmware Load”  
2
AddrL Starting address  
3
wValueH  
AddrH  
4
wIndexL  
0x00  
5
wIndexH  
0x00  
6
wLengthL  
wLengthH  
LenL Number of bytes  
7
LenH  
Table 7-22. Firmware Upload  
Byte  
0
Field  
bmRequestType  
bRequest  
wValueL  
Value  
Meaning  
8051 Response  
None Required  
0xC0 Vendor Request, IN  
0xA0 Firmware Load”  
AddrL Starting address  
AddrH  
1
2
3
wValueH  
4
wIndexL  
0x00  
5
wIndexH  
0x00  
6
wLengthL  
wLengthH  
LenL Number of Bytes  
LenH  
7
The EZ-USB core responds to two endpoint zero vendor requests, RAM Download and  
RAM Upload. These requests are active in all modes (ReNum=0 or 1).  
Because bit 7 of the first byte of the SETUP packet specifies direction, only one bRequest  
value (0xA0) is required for the upload and download requests. These RAM load com-  
mands are available to any USB device that uses the EZ-USB chip.  
A host loader program typically writes 0x01 to the CPUCS register to put the 8051 into  
RESET, loads all or part of the EZ-USB internal RAM with 8051 code, and finally reloads  
the CPUCS register with 0 to take the 8051 out of RESET. The CPUCS register is the  
only USB register that can be written using the Firmware Download command.  
EZ-USB TRM v1.9  
Chapter 7. EZ-USB CPU  
Page 7-23  
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