P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
tWC
Addresses
A0 to A20
tAS
tWP
tWR
WE#
tCW
CE#1
tCH
CE2
tBW
UB#, LB#
tCOE
tODW
tBE
High-Z
High-Z
DOUT
I/O1 to 16
tDS
Valid Data In
tDH
DIN
I/O1 to 16
(Note 1)
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 32. Pseudo SRAM Write Cycle—
UB#s and LB#s Control
58
Am49DL32xBG
July 19, 2002