P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
tWC
Addresses
A0 to A20
tAS
tWP
tWR
WE#
tCW
CE#1
tCH
CE2
tBW
LB#, UB#
tBE
tODW
D
OUT
High-Z
High-Z
I/O1 to 16
tCOE
tDS
tDH
D
IN
(Note 1)
(Note 1)
Valid Data In
I/O1 to 16
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 31. Pseudo SRAM Write Cycle—CE1#s Control
July 19, 2002
Am49DL32xBG
57