P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed
JEDEC
tAVAV
Std
tWC
tAS
Description
70
85
Unit
ns
Write Cycle Time (Note 1)
Min
Min
Min
Min
70
85
tAVWL
Address Setup Time
0
ns
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
ns
tWLAX
40
40
45
45
ns
Address Hold Time From CE#f or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
ns
ns
ns
Data Hold Time
0
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tWLEL
tELWL
tWS
tCS
WE# Setup Time (CE#f to WE#)
CE#f Setup Time
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
tEHWH
tWHEH
tWLWH
tWHDL
tWH
WE# Hold Time (CE#f to WE#)
CE#f Hold Time
tCH
tWP
Write Pulse Width
30
35
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
Byte
30
0
5
tWHWH1
tWHWH1 Programming Operation (Note 2)
µs
µs
Word
7
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
Typ
4
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Max
0.4
50
0
sec
µs
tVCS
tRB
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
ns
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
July 19, 2002
Am49DL32xBG
45
CYPRESS [ CYPRESS ]
