P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed
JEDEC
tAVAV
Std. Description
Test Setup
70
85
85
85
85
40
35
Unit
ns
tRC
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
70
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tACC Address to Output Delay
CE#f, OE# = VIL
OE# = VIL
70
70
30
30
ns
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
ns
Output Enable to Output Delay
ns
Chip Enable to Output High Z (Notes 1, 3)
Output Enable to Output High Z (Notes 1, 3)
ns
30
0
ns
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
ns
ns
ns
Read
0
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
Data# Polling
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 19 for test specifications
3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the
data bus driven to VCC/2 is taken as tDF
.
tRC
Addresses Stable
tACC
Addresses
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
42
Am49DL32xBG
July 19, 2002
CYPRESS [ CYPRESS ]
