D A T A S H E E T
After the system writes the autoselect command In the CMOS and TTL/NMOS-compatible DC Charac-
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more
information.
teristics tables, I
specification.
represents the standby current
CC3
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t the
RP,
device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
I
in the DC Characteristics table represents the
CC2
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
Current is reduced for the duration of the RESET#
bits on DQ7–DQ0. Standard read cycle timings and I
pulse. When RESET# is held at V , the device enters
CC
IL
read specifications apply. Refer to “The Erase Resume
command is valid only during the Erase Suspend
mode.” for more information, and to “AC Characteris-
tics” for timing diagrams.
the TTL standby mode; if RESET# is held at V
V, the device enters the CMOS standby mode.
0.5
SS
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V ± 0.5 V.
CC
(Note that this is a more restricted voltage range than
V .) The device enters the TTL standby mode when
within a time of t
(not during Embedded Algo-
IH
READY
CE# and RESET# pins are both held at V . The device
rithms). The system can read data t
after the
IH
RH
requires standard access time (t ) for read access
RESET# pin returns to V .
CE
IH
when the device is in either of these standby modes,
before it is ready to read data.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 10 for the timing diagram.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
Output Disable Mode
When the OE# input is at V , output from the device is
IH
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
disabled. The output pins are placed in the high imped-
ance state.
November 11, 2009 21505E8
Am29F400B
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CYPRESS [ CYPRESS ]
