欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM29F002BB-90EK 参数 Datasheet PDF下载

AM29F002BB-90EK图片预览
型号: AM29F002BB-90EK
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 256KX8, 90ns, PDSO32, LEAD FREE, MO-142BBD, TSOP-32]
分类和应用: 光电二极管内存集成电路
文件页数/大小: 40 页 / 1039 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号AM29F002BB-90EK的Datasheet PDF文件第6页浏览型号AM29F002BB-90EK的Datasheet PDF文件第7页浏览型号AM29F002BB-90EK的Datasheet PDF文件第8页浏览型号AM29F002BB-90EK的Datasheet PDF文件第9页浏览型号AM29F002BB-90EK的Datasheet PDF文件第11页浏览型号AM29F002BB-90EK的Datasheet PDF文件第12页浏览型号AM29F002BB-90EK的Datasheet PDF文件第13页浏览型号AM29F002BB-90EK的Datasheet PDF文件第14页  
D A T A S H E E T  
Status” for more information, and to each AC Charac-  
teristics section for timing diagrams.  
RESET#: Hardware Reset Pin  
Note: The RESET# pin is not available on the  
Am29F002NB.  
Standby Mode  
The RESET# pin provides a hardware method of reset-  
ting the device to reading array data. When the system  
When the system is not reading or writing to the device,  
it can place the device in the standby mode. In this  
mode, current consumption is greatly reduced, and the  
outputs are placed in the high impedance state, inde-  
pendent of the OE# input.  
drives the RESET# pin low for at least a period of t ,  
RP  
the device immediately terminates any operation in  
progress, tristates all data output pins, and ignores all  
read/write attempts for the duration of the RESET#  
pulse. The device also resets the internal state  
machine to reading array data. The operation that was  
interrupted should be reinitiated once the device is  
ready to accept another command sequence, to  
ensure data integrity.  
The device enters the CMOS standby mode when CE#  
and RESET# pins (CE# only on the Am29F002NB) are  
both held at V  
0.5 V. (Note that this is a more  
CC  
restricted voltage range than V .) The device enters  
IH  
the TTL standby mode when CE# and RESET# pins  
(CE# only on the Am29F002NB) are both held at V .  
IH  
Current is reduced for the duration of the RESET#  
The device requires standard access time (t ) for read  
CE  
pulse. When RESET# is held at V , the device enters  
IL  
access when the device is in either of these standby  
modes, before it is ready to read data.  
the TTL standby mode; if RESET# is held at V  
SS  
0.5 V, the device enters thCMOS standby mode.  
The device also enters the standby mode when the  
RESET# pin is driven low. Refer to the next section,  
“RESET#: Hardware Reset Pin”.  
The RESET# pin may be tied to the system reset cir-  
cuitry. A system et would thus also reset the Flash  
memory, enabling the system to read the boot-up firm-  
ware from the Flash memory.  
If the device is deselected during erasure or program-  
ming, the device draws active current until the  
operation is completed.  
Refer to the AC Characteristics tables for RESET#  
parameters and timing diagram.  
In the DC Characteristics tables, I  
standby current specification.  
represents the  
CC3  
Output Disable Mode  
When the OE# input is at V , output from the device is  
IH  
disabled. The output pins are placed in the high imped-  
ance state.  
Table 2. Am29F002B/Am29F002NB Top Boot Block Sector Address Table  
Sector Size  
(Kbytes)  
Address Range  
Sector  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
A17  
0
A16  
0
A15  
X
A14  
X
A13  
X
(in hexadecimal)  
00000h–0FFFFh  
10000h–1FFFFh  
20000h–2FFFFh  
30000h–37FFFh  
38000h–39FFFh  
3A000h–3BFFFh  
3C000h–3FFFFh  
64  
64  
64  
32  
8
0
X
X
X
1
0
X
X
X
1
1
0
X
X
1
1
1
0
0
1
1
1
0
1
8
1
1
1
1
X
16  
November 17, 2009 21527D8  
Am29F002B/Am29F002NB  
9
 复制成功!