ACM100
Progressive Scan Output Option
Figure 4. Progressive Scan Output Option
Vertical Blanking Interval
Field 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
525
21
Field 2
264
265
266
267
268
269
270
271
272
273 274
275
276
277 278
279 280
281
282
262
28
Serial Control Interface
by a single ACKnowledge bit which is driven by the receiver of
the previous 8 data bits.
The ACM100 utilizes the I2C bus to control and provide status
from an application. The I2C bus is a standard two wire serial
bus with data rates up to 400,000 bits per second.
Data transfer is initiated with a START condition. The START
condition is indicated when the SDAT signal goes low while
SCLK remains high. The START condition may be initiated at
anytime during a transfer and the ACM100 will restart the
transfer to begin accepting the DEVICE ADDRESS which
must immediately follow the START.
The two interface signals are called SCLK and SDAT. SCLK
provides a clock for asserting and sampling the SDAT signal.
SCLK is unidirectional from the bus master, typically an image
processing chip, to the ACM100. SDAT is the data bus and is
bi-directional. Both signals are open-drain and require a pullup
resistor of 1.5K Ohms.
The SDAT line must only transition when SCLK is low when
data is being transferred. If SDAT transitions while SCLK is
high, then it will be interpreted as either a START or a STOP
condition. Sufficient timing margins must be provided around
the rising and falling edges of SCLK to insure that a START or
STOP condition is not mistakenly recognized.
Data is always transmitted with the Most-Significant-Bit (MSB)
first. Eight bits of data are always transferred and are followed
Figure 5
START
ACK
A
STOP
6
5
4
3
2
1
0
7
SDAT
SCLK
The DEVICE ADDRESS is a sequence of 7 bits, a
READ/WRITE bit and an ACKnowledge bit. Data is always
transmitted MSB first and LSB last as shown in Figure 6. The
DEVICE ADDRESS is 7 bits long and must be 1110_011
(0xE6). The LSB of the first byte is the READ/WRITE bit where
a high (1) indicates that a READ cycle will follow and a low (0)
indicates that a write cycle will follow. After the READ/WRITE
bit, the ACM100 will assert SDAT low shortly after SCLK goes
low to acknowledge that the DEVICE ADDRESS has been
recognized and the ACM100 is ready to process the command
that follows. If the I2C bus master does not receive an
acknowledge bit, it should restart the transaction as the
ACM100 did not recognize its DEVICE ADDRESS
If a read transaction has been requested (READ/WRITE is
high), then the ACM100 will begin driving SDAT with the
register data at the current address. If a write transaction has
been requested then the bus master should send the REG
ADDRESS byte. The REG ADDRESS byte specifies which
register in the ACM100 is to be accessed.
The next two bytes of data are the write data where the MSB
is sent first and the LSB second. Upon completion of all data
being transferred, the master should issue a STOP command
to place the I2C interface in an idle state. A STOP command
is initiated by first driving SDAT low and SCLK high, then
bringing SDAT high while SCLK remains high.
Figure 6
DEVICE ADDRESS
1
1
6
1
0
0
1
1
1
START
R/W
0
ACK
A
5
4
3
2
7
SDAT
SCLK
Document Number: 001-05325 Rev. **
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