CY7C4282V
CY7C4292V
Switching Waveforms (continued)
WriteProgrammable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
ENS
ENH
LD
t
ENS
WEN
t
t
DH
DS
D –D
0
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
4282V–14
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
LD
t
t
ENS
ENH
t
ENS
PAF OFFSET
MSB
REN
t
A
PAF OFFSET
LSB
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
Q
–Q
15
0
4282V–15
[23, 24, 25]
Retransmit Timing
FL/RT
t
PRT
t
RTR
REN/WEN
EF/FF
4282V–16
Notes:
23. Clocks are free-running in this case.
24. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR
.
25. For the synchronous PAE and PAF flags an appropriate clock cycle is necessary after tRTR to update these flags.
10
CYPRESS [ CYPRESS ]
