CY7C374i
Functional Description
(continued)
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
Like all members of the F
LASH
370i family, the CY7C374i is rich
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 64 I/O pins on the
CY7C374i. In addition, there is one dedicated input and four
input/clock pins.
Finally, the CY7C374i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the type of application, the timing parameters
on the CY7C374i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370i family. The CY7C374i includes eight logic blocks.
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C374i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with F
LASH
370i.”
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term dis-
tribution.
3.3V or 5.0V I/O Operation
The F
LASH
370i family can be configured to operate in both 3.3V
and 5.0V systems. All devices have two sets of V
CC
pins: one
set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems.
When V
CCIO
pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability
is available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
LASH
370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
CC
or GND.
Design Tools
Development software for the CY7C371i is available from Cy-
press’s
Warp2®, Warp2Sim™,
and
Warp3®
software packag-
es. All of these products are based on the IEEE-standard
VHDL language. Cypress also actively supports third-party de-
sign tools from companies such as Synopsys, Mentor Graph-
ics, Cadence, and Synario. Please refer to third-party tool sup-
port for further information.
Product Term Array
The product term array in the F
LASH
370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in single passes
through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
LASH
370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Half of the macrocells on the CY7C374i have I/O pins associ-
ated with them. The input to the macrocell is the sum of be-
tween 0 and 16 product terms from the product term allocator.
The I/O macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and two
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the addi-
tion of input register capability. The user can program the bur-
ied macrocell to act as an input register (D-type or latch)
whose input comes from the I/O pin associated with the neigh-
4
CYPRESS [ CYPRESS SEMICONDUCTOR ]
