fax id: 6139
CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
•
•
•
•
128 macrocells in eight logic blocks
64 I/O pins
5 dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f
MAX
= 125 MHz
— t
PD
= 10 ns
— t
S
= 5.5 ns
•
•
•
•
— t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
Pin compatible with the CY7C373i
Functional Description
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i™ family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C374i is de-
signed to bring the ease of use as well as PCI Local Bus Spec-
ification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic™ F
LASH
370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally, be-
cause of the superior routability of the F
LASH
370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
CLOCK
INPUTS INPUTS
1
INPUT
MACROCELL
4
I/O
0
–I/O
7
8 I/Os
LOGIC
BLOCK
36
16
36
16
36
16
36
16
PIM
4
INPUT/CLOCK
MACROCELLS
4
36
16
36
16
36
16
36
16
LOGIC
BLOCK
8 I/Os
I/O
56
–I/O
63
Logic Block Diagram
A
8 I/Os
LOGIC
BLOCK
H
LOGIC
BLOCK
8 I/Os
I/O
8
–I/O
15
B
8 I/Os
LOGIC
BLOCK
G
LOGIC
BLOCK
8 I/Os
I/O
48
–I/O
55
I/O
16
–I/O
23
C
8 I/Os
LOGIC
BLOCK
F
LOGIC
BLOCK
8 I/Os
I/O
40
–I/O
47
I/O
24
–I/O
31
D
32
E
32
I/O
32
–I/O
39
7C374i-1
Selection Guide
7C374i–125
Maximum Propagation Delay
[1]
, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output
[1]
, t
CO
(ns)
Typical Supply Current, I
CC
(mA)
10
5.5
6.5
125
7C374i–100
12
6
7
125
7C374i–83
15
8
8
125
7C374i–66
20
10
10
125
7C374iL–66
20
10
10
75
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
October 1995 – Revised December 19, 1997
CYPRESS [ CYPRESS SEMICONDUCTOR ]
