欢迎访问ic37.com |
会员登录 免费注册
发布采购

7C1041AV33-10 参数 Datasheet PDF下载

7C1041AV33-10图片预览
型号: 7C1041AV33-10
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×16静态RAM [256K x 16 Static RAM]
分类和应用:
文件页数/大小: 9 页 / 142 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
 浏览型号7C1041AV33-10的Datasheet PDF文件第1页浏览型号7C1041AV33-10的Datasheet PDF文件第2页浏览型号7C1041AV33-10的Datasheet PDF文件第3页浏览型号7C1041AV33-10的Datasheet PDF文件第5页浏览型号7C1041AV33-10的Datasheet PDF文件第6页浏览型号7C1041AV33-10的Datasheet PDF文件第7页浏览型号7C1041AV33-10的Datasheet PDF文件第8页浏览型号7C1041AV33-10的Datasheet PDF文件第9页  
PRELIMINARY
Switching Characteristics
[5]
Over the Operating Range
7C1041AV33-10/
GVT73256A16-10
Parameter
READ CYCLE
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
ABE
t
LZBE
t
HZBE
t
PU
t
PD
WRITE CYCLE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP2
t
WP1
t
DS
t
DH
t
LZWE
t
HZWE
t
BW
WRITE Cycle Time
Chip Enable to End of Write
Address Valid to End of Write, with OE HIGH
Address Set-up Time
Address Hold from End of Write
WRITE Pulse Width
WRITE Pulse Width, with OE HIGH
Data Set-up Time
Data Hold Time
Write Disable to Output in Low-Z
Byte Enable to End of Write
[6, 7]
CY7C1041AV33/
GVT73256A16
7C1041AV33-12/
GVT73256A16-12
Min.
12
Max.
Unit
ns
102
12
3
3
ns
ns
ns
ns
6
6
0
6
6
0
6
0
12
12
8
8
0
0
10
8
6
0
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
8
ns
ns
Description
READ Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
[6, 7]
Chip Disable to Output in High-Z
[6, 7, 8]
Output Enable Access Time
Output Enable to Output in Low-Z
Output Enable to Output in High-Z
[6, 8]
Byte Enable Access Time
Byte Enable to Output in Low-Z
[6, 7]
Min.
10
Max.
10
10
3
3
5
5
0
5
5
0
5
0
10
10
8
8
0
0
10
8
5
0
3
5
8
Byte Disable to Output in High-Z
[6, 7, 8]
Chip Enable to Power-up Time
[6]
Chip Disable to Power-down Time
[6]
Write Enable to Output in High-Z
[6, 7, 8]
Data Retention Characteristics
Over the Operating Range (For L version only)
Parameter
V
DR
I
CCDR[9]
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V
CE > V
CC
– 0.2V;
all other inputs < V
SS
+ 0.2 or
V
CC
= 3V
>V
CC
– 0.2; all inputs static; f = 0
0
t
RC
Conditions
Min.
2.0
0.2
0.3
1.6
2.4
Typ.
Max.
Unit
V
mA
mA
ns
ns
t
CDR[6]
t
R[6, 10]
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes:
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
.
8. Output loading is specified with C
L
=5 pF as in AC Test Loads. Transition is measured ±500mV from steady state voltage.
9. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Loads.
10. t
RC
= Read Cycle Time.
4