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7C1041AV33-10 参数 Datasheet PDF下载

7C1041AV33-10图片预览
型号: 7C1041AV33-10
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×16静态RAM [256K x 16 Static RAM]
分类和应用:
文件页数/大小: 9 页 / 142 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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33
PRELIMINARY
CY7C1041AV33/
GVT73256A16
256K x 16 Static RAM
Features
Fast access times: 10, 12 ns
Fast OE access times: 5, 6, and 7 ns
Single +3.3V ±0.3V power supply
Fully static—no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise
immunity
Easy memory expansion with CE and OE options
Automatic CE power-down
High-performance, low power consumption, CMOS
double-poly, double-metal process
Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil
TSOP
Functional Description
The CY7C1049AV33\GVT73512A8 is organized as a 262,144
x 16 SRAM using a four-transistor memory cell with a high-per-
formance, silicon gate, low-power CMOS process. Cypress
SRAMs are fabricated using double-layer polysilicon, dou-
ble-layer metal technology.
This device offers center power and ground pins for improved
performance and noise immunity. Static design eliminates the
need for external clocks or timing strobes. For increased sys-
tem flexibility and eliminating bus contention problems, this de-
vice offers Chip Enable (CE), separate Byte Enable controls
(BLE and BHE) and Output Enable (OE) with this organization.
The device offers a low-power standby mode when chip is not
selected. This allows system designers to meet low standby
power requirements.
Functional Block Diagram
VCC
VSS
BLE#
Pin Configuration
SOJ/TSOP II
Top View
A0
DQ1
ADDRESS BUFFER
MEMORY ARRAY
512 ROWS X 256 X 16
COLUMNS
DQ8
DQ9
DQ16
A16
COLUMN DECODER
POWER
DOWN
CE#
BHE#
WE#
OE#
A
0
A
1
A
2
A
3
A
4
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
CC
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
17
A
16
A
15
OE
BHE
BLE
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
CC
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
14
A
13
A
12
A
11
A
10
ROW DECODER
Selection Guide
CY7C1049AV33-10/
GVT73512A8-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Com’l/Ind’l
Com’l
L
10
240
10
3.0
CY7C1049AV33-12/
GVT73512A8-12
12
210
10
3.0
Cypress Semiconductor Corporation
3901 North First Street
I/O CONTROL
San Jose
CA 95134
408-943-2600
June 15, 2000