Ultra37000 CPLD Family
Logic Block Diagrams
CY37032/CY37032V
Clock/
Input
Input
1
TDI
TCK
TMS
JTAG Tap
Controller
TDO
4
JTAG
EN
4
4
36
16
36
16
LOGIC
BLOCK
A
LOGIC
BLOCK
B
16 I/Os
16 I/Os
15
I/O −I/O
I/O −I/O
16
31
PIM
0
16
16
Clock/
Input
CY37064/CY37064V (100-Lead TQFP)
Input
4
1
4
4
36
36
LOGIC
BLOCK
LOGIC
BLOCK
D
16 I/Os
16 I/Os
16 I/Os
I/O -I/O
0
I/O -I/O
48
15
16
36
16
16
36
63
A
PIM
16 I/Os
LOGIC
BLOCK
B
LOGIC
BLOCK
C
I/O -I/O
32
I/O -I/O
16
16
47
31
32
32
TDI
JTAG Tap
Controller
TCK
TMS
TDO
Document #: 38-03007 Rev. *D
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