STK12C68
SOFTWARE-CONTROLLED
STORE/RECALL
CYCLE
SYMBOLS
NO.
Standard
33
t
AVAV
t
AVEL
t
ELEH
t
ELAX
t
RECALL
Alternate
t
RC
t
AS
t
CW
STORE/RECALL
Initiation Cycle
Time
Address Set-up Time
Clock Pulse Width
Address Hold Time
RECALL
Duration
PARAMETER
MIN
25
0
20
20
20
MAX
MIN
35
0
25
20
20
MAX
MIN
45
0
30
20
20
MAX
MIN
55
0
30
20
20
MAX
ns
ns
ns
ns
μs
p
u
u
u
STK12C68-25
STK12C68-35
(V
CC
= 5.0V
±
10%)
STK12C68-45
STK12C68-55
UNITS NOTES
34
35
36
37
Note u: The software sequence is clocked with E controlled READs.
Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a
STORE
cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a
RECALL
cycle. W must be high during all six consecutive cycles.
SOFTWARE
STORE/RECALL
CYCLE:
E Controlled
t
AVAV
ADDRESS
ADDRESS #1
33
t
AVAV
ADDRESS #6
33
t
AVEL
E
34
t
ELEH
35
t
ELAX
28
37
/
t
RECALL
36
t
STORE
DQ (DATA OUT)
DATA VALID
DATA VALID
HIGH IMPEDANCE
March 2006
7
Document Control # ML0008 rev 0.5
CYPRESS [ CYPRESS SEMICONDUCTOR ]
