STK12C68
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
1
2
3
4
5
6
7
8
9
10
11
t
ELQV
t
AVAVg
t
AVQVh
t
GLQV
t
AXQXh
t
ELQX
t
EHQZi
t
GLQX
t
GHQZi
t
ELICCHf
t
EHICCLf
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
35
5
5
10
0
10
0
45
25
25
10
5
5
10
0
12
0
55
PARAMETER
MIN
MAX
25
35
35
15
5
5
12
0
12
MIN
MAX
35
45
45
20
5
5
12
MIN
MAX
45
55
55
35
MIN
MAX
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK12C68-25
STK12C68-35
(V
CC
= 5.0V
±
10%)
STK12C68-45
STK12C68-55
UNITS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
3
t
AVQV
DATA VALID
SRAM READ CYCLE #2:
E Controlled
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
11
G
4
t
GLQV
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
t
ELICCH
I
CC
STANDBY
10
DATA VALID
8
ACTIVE
March 2006
3
Document Control # ML0008 rev 0.5
CYPRESS [ CYPRESS SEMICONDUCTOR ]
