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5962-9061102XX 参数 Datasheet PDF下载

5962-9061102XX图片预览
型号: 5962-9061102XX
PDF下载: 下载PDF文件 查看货源
内容描述: 32宏单元MAX® EPLD [32-Macrocell MAX® EPLD]
分类和应用: 可编程逻辑输入元件LTE时钟
文件页数/大小: 15 页 / 579 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
CY7C344
32-Macrocell MAX
®
EPLD
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double-metal CMOS EPROM technology
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
densest EPLD of this size. Eight dedicated inputs and 16
bidirectional I/O pins communicate to one logic array block. In
the CY7C344 LAB there are 32 macrocells and 64 expander
product terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
The speed and density of the CY7C344 makes it a natural for
all types of applications. With just this one device, the designer
can implement complex state machines, registered logic, and
combinatorial “glue” logic, without using multiple chips. This
architectural flexibility allows the CY7C344 to replace
multichip TTL solutions, whether they are synchronous,
asynchronous, combinatorial, or all three.
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded
ceramic chip carrier (HLCC), the CY7C344 represents the
Logic Block Diagram
15(22)
15(23)
27(6)
28(7)
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
1(8)
13(20)
14(21)
INPUT/CLK 2(9)
Pin Configurations
HLCC
Top View
I/O
I/O
I/O
VCC
GND
I/O
I/O
4 3 2 1 28 27 26
I/O
I/O
I
O
C
O
N
T
R
O
L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3(10)
4(11)
5(12)
6(13)
9(16)
10(17)
V
CC
GND
I/O
I/O
I/O
I/O
11(18)
12(19)
17(24)
18(25)
19(26)
20(27)
23(2)
24(3)
25(4)
26(5)
INPUT
INPUT/CLK
I/O
I/O
I/O
I/O
V
CC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
I/O
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
I/O
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
12 13 14 1516 1718
MACROCELL 2
MACROCELL 4
MACROCELL 6
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
G
L
O
B
A
L
B
U
S
MACROCELL 1
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
CerDIP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT
INPUT
I/O
I/O
I/O
I/O
V
CC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
64 EXPANDER PRODUCT TERM ARRAY
32
Selection Guide
7C344-15
Maximum Access Time
Maximum Operating Current
Commercial
Military
Industrial
Maximum Standby Current
Commercial
Military
Industrial
Note:
1. Numbers in () refer to J-leaded packages.
7C344-20
20
200
220
220
150
170
170
7C344-25
25
200
220
220
150
170
170
Unit
ns
mA
15
200
220
150
170
mA
Cypress Semiconductor Corporation
Document #: 38-03006 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised June 6, 2005