Delta39K™ ISR™
CPLD Family
Table 8. Pin Definition Table
Pin Name
Reconfig
TCLK
Function
Input
Description
Pin to start configuration of Delta39K
JTAG Test Clock
Input
TDI
Input
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
Operating Voltage
VCC for I/O bank 0
VCC for I/O bank 1
VCC for I/O bank 2
VCC for I/O bank 3
VCC for I/O bank 4
VCC for I/O bank 5
VCC for I/O bank 6
VCC for I/O bank 7
VCC for JTAG pins
VCC for Configuration port
VCC for PLL
TDO
Output
Input
TMS
VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Output
Output
Output
Input
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCJTAG
VCCCNFG
[18]
VCCPLL
VCCPRG
Config_Done
CCLK
VCC for programming the Self-Boot™ solution embedded boot PROM
Flag indicating that configuration is complete
Configuration Clock for serial interface with the external boot PROM
Chip select for the external boot PROM (active low)
CCE
Data
Pin to receive configuration data from the external boot PROM
Reset signal to interface with the external boot PROM
Reset
Output
Table 9. Mode Select (MSEL) Pin Connectivity Table
Table 10. I/O Banks for Global Clock and Global Control
Pins (in all densities and packages)
GND
Delta39K - Self-Boot™ Solution
GCLK[0]
GCTL[0]
GCLK[1]
GCTL[1]
GCLK[2]
GCTL[2]
GCLK[3]
GCTL[3]
VCCCNFG
Delta39K - with external boot PROM
Bank
0
5
6
7
Number
Table 11. 208 EQFP/PQFP Pin Table
Pin
1
CY39030
GCTL0
GND
CY39050
GCTL0
GND
CY39100
GCTL0
GND
CY39165
GCTL0
GND
CY39200
GCTL0
GND
GCLK0
GND
IO0
2
3
GCLK0
GND
GCLK0
GND
GCLK0
GND
GCLK0
GND
4
5
IO0
IO0
IO0
IO0
6
IO0
IO0
IO0
IO0
IO0
7
IO0
IO0
IO0
IO0
IO0
8
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
9
10
11
IO0
IO0
IO0
IO0
IO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
Note:
18. The PLL is available in Delta39K ‘V’ devices (2.5V/3.3V) and not in Delta39K ‘Z’ devices (1.8V). In Delta39K ‘Z’ devices, connect VCCPLL to VCC
.
Document #: 38-03039 Rev. *H
Page 46 of 86
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