Delta39K™ ISR™
CPLD Family
Package Diagrams (continued)
676-Ball FBGA (27 x 27 x 1.6 mm) BB676/MB676
51-85125-*B
Pin Tables
Table 8. Pin Definition Table
Pin Name
GCLK0-3
GCTL0-3
GND
Function
Input
Description
Global Clock signals 0 through 3
Global Control signals 0 through 3
Ground
Input
Ground
IO/VREF0
IO/VREF1
IO/VREF2
IO/VREF3
IO/VREF4
IO/VREF5
IO/VREF6
IO/VREF7
IO
Input/Output Dual function pin: IO or Reference Voltage for Bank 0
Input/Output Dual function pin: IO or Reference Voltage for Bank 1
Input/Output Dual function pin: IO or Reference Voltage for Bank 2
Input/Output Dual function pin: IO or Reference Voltage for Bank 3
Input/Output Dual function pin: IO or Reference Voltage for Bank 4
Input/Output Dual function pin: IO or Reference Voltage for Bank 5
Input/Output Dual function pin: IO or Reference Voltage for Bank 6
Input/Output Dual function pin: IO or Reference Voltage for Bank 7
Input/Output Input or Output pin
IO6/Lock
MSEL
Input/Output Dual function pin: IO in Bank 6 or PLL lock output signal
Input
Mode Select Pin (see Table 9)
Document #: 38-03039 Rev. *H
Page 45 of 86
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