Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory Internal Clocking 2
MACROCELL INPUT
CLOCK
tCHMMACS
FIFO READ
CLOCK
tMACCHMS
FIFO WRITE
CLOCK
tCHMMACF
FIFO READ OR
WRITE CLOCK
Channel Memory DP SRAM Flow-Through R/W Timing
CLOCK
tCHMCYC1
tCHMS
tCHMH
An+3
An+2
An–1
An
An+1
ADDRESS
WRITE
ENABLE
tCHMS
tCHMH
DATA
INPUT
Dn–1
Dn+1
Dn+3
tCHMDV1
tCHMDV1
tCHMDV1
tCHMDV1
Dn+1
Dn–1
Dn
Dn+2
Dn+3
OUTPUT
Document #: 38-03039 Rev. *H
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