Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory DP Asynchronous Timing
An+1
An+2
ADDRESS
An-1
An
tCHMHA
tCHMSA
tCHMPWE
WRITE
ENABLE
tCHMSD
tCHMHD
DATA
INPUT
Dn
tCHMAA
tCHMAA
Dn–1
OUTPUT
Dn+1
Dn
Channel Memory Internal Clocking
MACROCELL INPUT
CLOCK
tMACCHMS1
tCHMMACS1
CHANNEL MEMORY
INPUT CLOCK
tCHMMACS2
tMACCHMS2
CHANNEL MEMORY
OUTPUT CLOCK
Document #: 38-03039 Rev. *H
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