3.0 Circuit Descriptions
RS8953B/8953SPB
3.1 MPU Interface
HDSL Channel Unit
Figure 3-2. MPU Interrupt Logic
Read IMR
Mask
DATA
INTR*
Write IMR
Read IRR
Interrupt
Event
Set
Other Interrupt
Sources
Request
Reset
Write ICR
3.1.1 Address/Data Bus
Address/data bus pins AD[7:0] allow MPU access to RS8953B internal registers.
Read and write access is allowed at any of the 256 address locations, but only
defined register address locations are applicable (see Table 4-1).
3.1.2 Bus Controls
Five signals control register access: ALE, CS*, RD*, WR*, and MPUSEL. The
address on AD[7:0] is latched on the falling edge of ALE, and CS* is an
active-low port enable for all read and write operations. If CS* is high, the MPU
port is inactive.
Different styles of bus control are supported using separate read and write
strobes for Intel-style buses, or common data strobe with a combined read/write
signal for Motorola-style buses. When MPUSEL = 0 (Intel bus), RD* is an
active-low read enable and WR* is an active-low write strobe. While RD* and
CS* are low, the addressed register’s data is driven onto AD[7:0]. If WR* and
CS* are low, the rising edge of WR* or CS* latches data from AD[7:0] into the
register. When MPUSEL = 1 (Motorola bus), RD* is an active-low data strobe for
both read and write cycles, and WR* is a read/write select. While RD* and CS*
are low and WR* is high, the addressed register’s data is driven onto AD[7:0]. If
RD*, CS*, and WR* are low, the rising edge of RD*, CS*, or WR* latches data
from AD[7:0].
3-2
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
