3
3.0 Circuit Descriptions
3.1 MPU Interface
The Microprocessor Unit (MPU) interface consists of an 8-bit parallel
multiplexed address-data bus, an associated bus control signal, and a maskable
interrupt request output, as illustrated in Figure 3-1 and Figure 3-2. The MPU
interface is compatible with 8-bit processors running at bus cycle speeds up to
16 MHz. Systems that use 16 or 32-bit processors can add an external address
buffer and data transceiver to connect the RS8953B. Faster bus speeds require
external wait-state insertion logic.
Figure 3-1. MPU Bus Control Logic
ALE
Address
AD[7:0]
MPUSEL
RD*
To Registers
From Registers
Read Strobe
WR*
CS*
Write Strobe
N8953BDSB
Conexant
3-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
