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Label
I/O Type
Signal/Definition
OVERHEAD SIGNALS
CLKIN
I
Clock In. Connect to an external 28.224 MHz clock circuit.
~RES1,
~RES2
IA
Reset. ~RESET low holds the MDP in the reset state. ~RESET going high releases the MDP from the reset
state and initiates normal operation using power turn-on (default) values. ~RESET must be held low for at least
3 µs. The MDP is ready to use 400 ms after the low-to-high transition of ~RESET. ~RES1 and ~RES2 are
typically connected to the MCU ~RESET input and to the host bus ~RESET (or RESET through an inverter) line
(parallel host) or reset circuit (serial DTE interface) which resets both the MCU and MDP upon power turn-on.
~RES1 and ~RES2 have active internal pull-up resistors.
~WKRES
IA
Wake-up Reset. ~WKRES is connected internally to ~RESET but will not drive the MDP ~RESET pins.
Asserting ~WKRES performs the same reset function as the MDP ~RESET and typically used by the MCU to
wake up the MDP from SLEEP Mode when the MDP ~RESET lines cannot be asserted (because they are also
connected to the MCU ~RESET input). For a serial DTE or parallel host MCU configuration, connect ~WKRES to
the MCU ~WKRESOUT output. ~WKRES has an active internal pull-up resistor.
VDD
PWR
PWR
PWR
REF
GND
GND
OA
+3.3V Digital Circuit Power Supply. Connect to +3.3V through digital circuit power supply filter.
+3.3V Analog Circuit Digital Power Supply. Connect to +3.3V through digital circuit power supply filter.
Analog Circuit Analog Power Supply. Connect to +5V through analog circuit power supply filter.
Input Reference Voltage. Reference voltage for +5V tolerant input pins. Connect to +5V.
Digital Ground. Connect to digital ground.
AVDD
AVAA
VGG
GND
AGND
XCLK
Analog Ground. Connect to analog ground.
X Clock. Output clock at 56.448 MHz (PLL disabled) or 63.5045 (PLL enabled), which runs during MDP Normal
Mode and is turned off during Sleep Mode.
YCLK
OA
Y Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and is turned off during Sleep
Mode.
SYCLK
OA
System Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and during Sleep Mode.
PLLVDD Connection. Connect to +3.3V (VDD) through 10 Ω and to DGND through 10 (+) µF.
PLLGND Connection. Connect to DGND.
PLLVDD
PLLGND
PLL
PLL
PARALLEL HOST INTERFACE
Address, data, control, and interrupt hardware interface signals allow MDP connection to an 8086-compatible microprocessor bus. With the
addition of external logic, the interface can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or
68000. The microprocessor interface allows a microprocessor to change MDP configuration, read or write channel and diagnostic data, and
supervise MDP operation by writing control bits and reading status bits.
D0–D7
IA/OB
Data Lines. Eight bidirectional data lines (D0–D7) provide parallel transfer of data between the host and the
MDP. The most significant bit is D7. Data direction is controlled by the Read Enable and Write Enable signals.
RS0–RS4
IA
Register Select Lines. The five active high register select lines (RS0–RS4) address interface memory registers
within the MDP interface memory. These lines are typically connected to the five least significant lines (A0–A4)
of the address bus.
The MDP decodes RS0 through RS4 to address one of 32 internal interface memory registers (00–1F). The
most significant address bit is RS4, while the least significant address bit is RS0. The selected register can be
read from or written into via the 8-bit parallel data bus (D0–D7). The most significant data bit is D7, while the
least significant data bit is D0.
~CS
IA
IA
Chip Select. ~CS selects the MDP for microprocessor bus operation. ~CS is typically generated by decoding
host address bus lines.
~READ
Read Enable. During a read cycle (~READ asserted), data from the selected interface memory register is gated
onto the data bus by means of three-state drivers in the MDP. These drivers force the data lines high for a one
bit, or low for a zero bit. When not being read, the three-state drivers assume their high-impedance (off) state.
~WRITE
IRQ
IA
Write Enable. During a write cycle (~WRITE asserted), data from the data bus is copied into the selected MDP
interface memory register, with high and low bus levels representing one and zero bit states, respectively.
OA
Interrupt Request. The MDP IRQ output may be connected to the host processor interrupt request input in
order to interrupt host program execution for immediate MDP service. The IRQ output can be enabled in the
MDP interface memory to indicate immediate change of conditions. The use of IRQ is optional depending upon
MDP application. The IRQ output is driven by a TTL-compatible CMOS driver.
CONEXANT [ CONEXANT SYSTEMS, INC ]
