CY74FCT2374T
8-BIT REGISTER
WITH 3-STATE OUTPUTS
SCCS040A – SEPTEMBER 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
2.4
20
TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 4.75 V,
I
I
I
I
= –18 mA
–0.7
3.3
0.3
25
–1.2
IK
CC
CC
CC
CC
IN
= –15 mA
= 12 mA
= 12 mA
V
OH
OL
OH
OL
OL
0.55
40
V
R
Ω
OUT
hys
V
All inputs
0.2
V
I
I
I
I
I
I
I
I
V
V
V
V
V
V
V
V
V
V
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
= V
CC
5
±1
µA
µA
µA
µA
µA
mA
µA
mA
mA
I
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IN
IN
IN
= 2.7 V
= 0.5 V
IH
±1
IL
= 2.7 V
= 0.5 V
= 0 V
10
OZH
OZL
OUT
OUT
OUT
OUT
–10
–225
±1
‡
–60
–120
OS
= 4.5 V
off
= 5.25 V,
≤ 0.2 V,
V ≥ V
IN CC
– 0.2 V
0.1
0.5
0.2
2
CC
IN
§
∆I
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
CC
1
= 5.25 V, Outputs open, One input switching at 50% duty cycle,
– 0.2 V
mA/
MHz
¶
I
0.06
0.12
CCD
OE = GND, V ≤ 0.2 V or V ≥ V
IN IN CC
V
V
≤ 0.2 V or
One bit switching
IN
IN
0.7
1.2
1.6
1.4
3.4
≥ V
CC
– 0.2V
at f = 5 MHz
1
V
= 5.25 V,
CC
Outputs open,
= 10 MHz,
at 50% duty cycle
Eight bits switching
V
IN
= 3.4 V or GND
#
I
C
mA
f
0
V
IN
V
IN
≤ 0.2 V or
||
||
3.2
OE = GND
≥ V
– 0.2 V
at f = 2.5 MHz
1
at 50% duty cycle
CC
V
IN
= 3.4 V or GND
3.9
5
12.2
C
C
10
12
pF
pF
i
9
o
†
‡
Typical values are at V
CC
= 5 V, T = 25°C.
A
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, I
tests should be performed last.
OS
§
¶
#
Per TTL-driven input (V = 3.4 V); all other inputs at V
or GND
IN CC
This parameter is derived for use in total power-supply calculations.
= I + ∆I × D × N + I (f /2 + f × N )
I
C
CC
CC
H
T
CCD
0
1
1
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
C
CC
CC
H
T
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
4
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