CX82100 Home Network Processor Data Sheet
1.3.6
ASB Slaves
ASB slaves respond to read or write operations within a given address-space range. A bus
slave signals the success, failure, or waiting of the data transfer back to the active master.
The ASB slaves in the HNP ASIC are the ARM940T (test mode only), EMC, ASB-to-
APB Bridge/DMAC, internal ROM, and internal SRAM.
Detailed discussion of the AMBA signals and protocols may be found in Reference [3].
ARM940T Slave
The ARM940T slave has one 32-bit test-mode register that can be accessed by the TIC
during test mode.
External Memory Controller Slave
The External Memory Controller (EMC) controls all external SDRAM/SRAM accesses.
The SDRAM/SRAM is programmed by the EMC to transfer a burst of four data bytes.
The configuration registers for the EMC reside in the Host Control Register
(HST_CTRL) and the External Memory Control Register (EMCR).
The SDRAM refresh controller is internal to the EMC. The EMC simply asserts the wait
response to the ASB if it is deselected (by the ASB Decoder) during the refresh. The
master requesting the memory access is held off with wait states for the duration of the
refresh operation.
ASB-to-APB Bridge/DMAC
The ASB-to-APB Bridge converts ASB transfers into a suitable format for the slave
devices on the APB. The bridge provides latching of all address, data, and control signals,
as well as provides a second level of decoding to generate slave select signals for the
APB peripherals. The bridge is a slave on the ASB and a master on the APB. All
peripherals on the APB are slaves only.
As an ASB slave, the DMAC is accessed by the ARM940T and the Host Interface
(including the TIC ASB master in test mode). Obviously, the master portion of the
DMAC also has access, not via the ASB but internal to the DMAC module. Note that the
DMAC is also a bus master on the APB.
Internal ROM
The internal 16k x 32 ROM provides high-speed read-only program and data for the
ARM940T. The ARM940T uses this internal ROM or external Flash ROM to run the
boot code upon the de-assertion of the reset signal.
The internal ROM code configures the UDC with configuration data read from an
optional I2C EEPROM or internal ROM. The internal ROM code initiates UDC setup by
communicating to the I2C EEPROM using the I2C_DATA (GPIO15) and I2C_CLOCK
(GPIO16) pins. Based on the signature byte read from the I2C EEPROM, the HNP uses
either I2C EEPROM data or internal ROM data to set up the UDC. See Section for
additional information.
Internal RAM
The internal 8k x 32 RAM provides high-speed read-write program and data for the
ARM940T.
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