CX82100 Home Network Processor Data Sheet
1.3.1
Advanced Microcontroller Bus Architecture
The HNP internal architecture is based on the Advanced Microcontroller Bus
Architecture (AMBA) which defines two internal busses, the Advanced System Bus
(ASB) and the Advanced Peripheral Bus (APB).
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The 32-bit ASB is a high performance, burst-mode, pipelined bus, which connects
multiple bus masters. The ASB supports internal interfaces to functions (blocks)
such as processor, on-chip memory, external memory controller, and DMA
controller.
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The 64-bit APB connects peripheral interface blocks to the ASB through the ASB-
to-APB Bridge/DMAC and is designed for minimal power consumption and reduced
complexity to support the system’s peripheral functions such as Timers, EMACs,
and the USB interface.
There are three other components of the AMBA system: the ASB Decoder, ASB Arbiter,
and the ASB-to-APB Bridge.
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The ASB Decoder decodes the addresses for all the ASB slave devices.
The ASB Arbiter assigns the ASB ownership to ASB masters.
All APB devices are accessible by ASB masters through the ASB-to-APB Bridge.
1.3.2
ARM940T Processor
The HNP uses an ARM940T Harvard Load/Store Architecture cached processor
macrocell with a high performance 32-bit RISC-based ARM9TDMI Core. The "TDMI"
stands for Thumb 16-bit compressed instruction set, Debug extensions, Multiplier
enhanced, and ICE extension.
Separate 4 kB instruction and 4 kB data caches and a memory protection unit allow the
memory to be segmented and protected in a simple manner. A write-back cache scheme
and write buffer are used to optimize performance and minimize ASB traffic.
The ARM940T uses a 5-stage pipeline consisting of fetch, decode, execute, memory and
write stages. The ARM940T interfaces to the other internal HNP blocks using unified
address and data busses compatible with the AMBA bus architecture. The ARM940T
also has a ‘TrackingICE’ mode that allows a conventional ICE (in-circuit emulator) mode
of operation.
The ARM9TDMI Core has two active-low and level-sensitive interrupt inputs, FIQ# and
IRQ#, which can occur asynchronously. The FIQ# is higher priority than IRQ# in that it
is serviced first when both interrupts assert simultaneously. Servicing an FIQ# disables
IRQ# until the FIQ# handler exits or re-enables IRQ#. An interrupt handler must always
clear the source of the interrupt. The vector addresses for IRQ# and FIQ# are
0x00000018 and 0x0000001C, respectively.
1.3.3
ASB Decoder
The ASB Decoder performs the address decoding and selects slaves appropriately.
1-6
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