CX82100 Home Network Processor Data Sheet
Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)
Pin Signal
EM1_TXER
Pin No.
I/O
O
I/O Type
Otts4
Signal Name/Description
LAN 1 Transmit Coding Error. When EM1_TXER is asserted for
one or more EM1_TX_CLK periods while EM1_TX_EN is also
asserted, the LAN 1 EPHY emits one or more symbols that are not
part of the valid data or delimiter set somewhere in the frame being
transmitted. Permissible encoding of EM1_TXER with EM1_TX_EN
and EM1_TXD[3:0] are:
G3
EM1_TX_EN EM1_TXER EM1_TXD[3:0]
Description
0
0
1
0
1
0
0000–1111 Normal Inter-Frame
0000–1111 Reserved
0000–1111 Normal Data
Transmission
1
1
0000–1111 Transmit Error
Propagation
For MII, connect to LAN 1 EPHY TXER pin.
For 7-WS interface, leave open.
EMAC 2 Interface
The EMAC 2 interface is the same as the EMAC 1 interface. Refer to the EMAC1 interface for signal definitions.
EM2_COL
EM2_CRS
EM2_MDC
EM2_MDIO
EM2_RX_CLK
EM2_RXD[3:0]
B8
J12
B6
A6
C8
I
I
Itpd
Itpd
Otts4
Itpd/Ot4
Itpd
LAN 2 Collision Indication.
LAN 2 Carrier Sense.
LAN 2 Management Data Clock.
LAN 2 Serial Management Data Input/Output.
LAN 2 Receive Clock.
O
I/O
I
I
E7, B7, A7,
Itpd
LAN 2 Receive Data.
A14
EM2_RXDV
EM2_RXER
EM2_TX_CLK
EM2_TX_EN
EM2_TXD[3:0]
C7
D7
L13
J13
I
I
I
O
O
Itpd
Itpd
Itpd
Otts4
Otts4
LAN 2 Receive Data Valid.
LAN 2 Receive Error
LAN 2 Transmit Clock.
LAN 2 Transmit Enable.
LAN 2 Transmit Data.
L14, L12, K12,
M14
EM2_TXER
K14
O
Otts4
LAN 2 Transmit Error.
2-12
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