CX82100 Home Network Processor Data Sheet
1.3.7
APB Functions
The Advanced Peripheral Bus (APB) provides signaling for I/O functions.
EMAC Interface
Dual Media Independent Interface (MII) or 7-Wire Serial (7-WS) interfaces, controlled
by two identical HNP 10/100BaseT Ethernet MAC (EMAC) blocks, optionally connect
interchangeably to devices such as an Ethernet transceiver PHY, Conexant CX24611
HomePNA 2.0 AFE/PHY, Conexant CX11647 HomePlug 1.0 device.
USB Interface
The USB controlled by the HNP USB Interface optionally connects to a PC or USB hub.
This interface complies with the Universal Serial Bus Specification Rev. 1.1 and operates
at USB full speed (12 Mbps). It acts as a USB slave device only, i.e., it cannot act as a
root hub).
General Purpose Input/Output Interface
Bidirectional general purpose input/output (GPIO) lines are controlled by the HNP GPIO
Interface. Most of these GPIO lines are used for the interfaces mentioned above in a fully
configured system.
Clock Generation
The Clock Generation block generates internal and external clocks using two
programmable, fractional multiply phase locked loop (PLL) blocks, FCLK_PLL and
BCLK_PLL. Included in each block is the actual PLL circuit including a voltage-
controlled oscillator (VCO), and post-PLL generation logic which divides the output of
each PLL to create a series of sub-multiple clocks.
Interrupt Controller
All peripheral interrupt sources are routed through the Interrupt Controller (INTC) and
reduced to one of two active low inputs to the ARM940T processor, fast interrupt (FIQ#)
or regular interrupt (IRQ#), as selected in the Interrupt Level Assignment Register
(INT_LA). No hardware-assisted priority scheme is implemented in the HNP other than
FIQ# having a higher priority than IRQ#. The system software must implement the
priority scheme for individual interrupts in the FIQ# and IRQ# exception handlers.
1.4
Development Kits
Please contact a local Conexant sales office for information about available development
kits using the CX82100 HNP.
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