CX82100 Home Network Processor Data Sheet
1.3.4
1.3.5
ASB Arbiter
The ASB Arbiter performs arbitration on the ASB to ensure that only one ASB master at
a time is allowed to initiate data transfers. No arbitration scheme is enforced, therefore,
either 'highest priority' or 'fair' access algorithms may be implemented, depending on the
application requirements.
ASB Masters
An ASB master can initiate read and write operations by providing address and control
information. The HNP contains three bus masters: the ARM940T, the Host Interface, and
the DMAC. Only one bus master is allowed to actively use the ASB at any one time. The
DMAC is both an ASB master and an APB master.
ARM940T Master
The ARM940T master transfers data to and from the internal ROM, internal SRAM, the
ASB-to-APB Bridge, and the external SDRAM/SRAM via the EMC. The ARM940T
master also transfers configuration register information directly to and from the DMAC.
DMAC Master
The DMAC master transfers data to and from the external SDRAM/SRAM via the EMC.
The EMC is the only ASB slave accessed by the DMAC master. The DMAC is integrated
with the ASB-to-APB Bridge because the DMAC is both an ASB master and an APB
master. Data transferred on the ASB is always a dword (32 bits). However, data
transferred on the APB is always a qword (64 bits) which requires valid data on the entire
64-bit APB data bus.
Host Interface Master
The Host Interface master transfers data over the Host Parallel Expansion Bus to and
from external Flash ROM and an optional peripheral (e.g., UART) via an internal
memory-mapped register set using two chip select/GPIO signals. The Host Interface
master operates asynchronously.
The Host Interface master can also be used as the Test Interface Controller (TIC) bus
master. The TIC is a low gate-count test interface module which allows externally
applied test vectors to be converted into internal bus transfers. The TIC can also be used
to read and write registers within the HNP from the external Host Interface pins. The TIC
uses a minimal 3-wire handshake mechanism (TREQA, TREQB, and TACK) to control
the application of test vectors and the data path of the EMC.
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