CX28394/28395/28398
4.0 Electrical/Mechanical Specifications
Quad/x16/Octal—T1/E1/J1 Framers
4.4 AC Characteristics
Table 4-5. Input Data Setup and Hold Timing
Symbol
Clock
Edge
Input Data
Minimum
Maximum
Units
1
MCLK
Rising
ONESEC
RST*
5
5
2
2
6
5
5
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
(tsetup
)
RCKI
Rising
Falling
RPOSI
RNEGI
TDLI
TDLCKO
RSBCKI
RSYN_NEG
(addr 0D1)
RMSYNC
RFSYNC
TPCMI
TSIGI
TSBCKI
TCKI(1)
TPCM_NEG
(addr 0D4)
5
5
5
—
—
—
ns
ns
ns
TSYN_NEG
(addr 0D4)
TFSYNC
TMSYNC
ONESEC
RST*
5
5
5
3
3
2
5
5
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
2
(thold
MCLK
RCKI
Rising
Rising
Falling
)
RPOSI
RNEGI
TDLCKO
RSBCKI
TDLI
RSYN_NEG
(addr 0D1)
RMSYNC
RFSYNC
TPCMI
TSIGI
TSBCKI
TCKI(1)
TPCM_NEG
(addr 0D4)
2
5
2
—
—
—
ns
ns
ns
(2)
TSYN_NEG
(addr 0D4)
TFSYNC
TMSYNC
2
—
ns
NOTE(S):
(1)
If the TSLIP buffer is bypassed (TSB_CR; addr OD4), TCKI is used; otherwise, TSBCKI is used.
100054E
Conexant
4-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
